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AMCC PPC405 Specifiche Pagina 35

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PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.08 – March 24, 2008
AMCC 35
Data Sheet
TDO Test data out. O
5V tolerant
3.3V LVTTL
TCK
JTAG test clock. The frequency of this input can range from DC to
25MHz.
I
5V tolerant
3.3V LVTTL
1, 4
TRST
JTAG reset. TRST must be low at power-on to initialize the JTAG
controller.
I
5V tolerant
3.3V LVTTL
5
System Interface
SysReset
Main system reset. External logic can drive this bidirectional pin low
(minimum of 16 cycles) to initiate a system reset. A system reset can
also be initiated by software. Implemented as an open-drain output
(two states; 0 or open circuit).
I/O
5V tolerant
3.3V LVTTL
1, 2
SysErr Set to 1 when a Machine Check is generated. O
5V tolerant
3.3V LVTTL
6
Halt
Halt from external debugger. I
5V tolerant
3.3V LVTTL
1, 2
GPIO00:31
General Purpose I/O. All of the GPIO signals are multiplexed with
other signals.
I/O
5V tolerant
3.3V LVTTL
1
TestEn
Test Enable. Used only for manufacturing tests. Pull down for normal
operation.
I
1.8V CMOS
w/pull-down
SysClk Main system clock input. I 3.3V LVTTL
[RejectPkt0:1] External request to reject a packet. I
5V tolerant
3.3V LVTTL
AV
DD
Clean voltage input for the PLL. I
AGND Clean Ground input for the PLL. I
Trace Interface
[TS1E]
[TS2E]
Even Trace execution status. To access this function, software must
toggle a DCR bit
O
5V tolerant
3.3V LVTTL
1
[TS1O]
[TS2O]
Odd Trace execution status. To access this function, software must
toggle a DCR bit
O
5V tolerant
3.3V LVTTL
1
[TS3:6] Trace status. To access this function, software must toggle a DCR bit O
5V tolerant
3.3V LVTTL
1
[TrcClk]
Trace interface clock. Operates at half the CPU core frequency. To
access this function, software must toggle a DCR bit
O
5V tolerant
3.3V LVTTL
1
Table 6. Signal Functional Description (Sheet 5 of 6)
Secondary multiplexed signals are shown in brackets.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 30.
Signal Name Description I/O Type
Notes
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